FIG. 1 is a block diagram illustrating a phase-locked loop (PLL) 100. The PLL 100 includes a voltage-controlled oscillator (VCO) and a frequency divider along with other components such as an N-divider, a phase frequency detector (PFD), a charge pump (CP), and a low-pass filter (LPF). In most cases, the PLL frequency is directly determined by its VCO tuning range, and a divide-by-two (div2) or divide-by-four (div4) frequency divider is used to generate an I/Q (in-phase/quadrature) clock at, respectively, half of or a quarter of the VCO frequency.
However, when the frequency range is relatively large and the VCO cannot achieve a two times (2X) tuning range without sacrificing power and phase noise performance, there can be a gap in the frequencies that can be provided by the PLL, especially at higher frequencies. For example, if the VCO has a frequency range of 14-21 gigahertz (GHz), then a div2 frequency divider will provide a frequency range of 7-10.5 GHz and a div4 frequency divider will provide a frequency range of 3.5-5.25 GHz, leaving a gap in the range of 5.25-7 GHz.
Some conventional PLL designs that require a quadrature clock solve this problem by incorporating multiple VCOs, each covering a different frequency range. However, the circuit overhead for those types of designs is large because they require extra clocks and extra multiplexers. Also, if inductor-capacitor (LC) VCOs are used, then the size of the PLL can be problematic because each LC VCO needs its own inductor coil and the inductor coils need to be spaced far enough apart from each other to eliminate any undesirable coupling effects.
Other conventional PLL designs employ a divide-by-three (div3) frequency divider to bridge the frequency gap with a single VCO. However, conventional div3 frequency dividers provide neither the preferred 50 percent duty cycle nor the preferred quadrature phase when the frequency is divided by three. Some designs use injection-locking div3 circuits to generate a 50 percent duty cycle with a passive polyphase filter for quadrature phase generation, but these can be problematic because they can only provide a narrow operating frequency range and do not suit applications in the 1.5× tuning range, which corresponds to the gap between divide-by-two and divide-by-four.